The present invention relates to a semiconductor device comprising at least one first semiconductor layer and a second layer applied on at least a surface portion of the first layer for protecting the device, said protecting layer being of a second material having a larger energy gap between the valence band and conduction band than a first material forming said first layer.
All types of semiconductor devices are comprised, such as for example different types of diodes, transistors and thyristors. xe2x80x9cSemiconductor devicexe2x80x9d is here to be interpretated very broadly and covers not only what is usually meant by this expression, but also integrated circuits and Multi Chip Module (MCM). Furthermore, xe2x80x9cprotectingxe2x80x9d includes different type of protection, such as against high electric fields, moisture, mechanical damage, chemical reactions and so on, so that this word includes xe2x80x9cinsulatingxe2x80x9d, xe2x80x9cpassivatingxe2x80x9d and xe2x80x9cprotectingxe2x80x9d as commonly used.
Accordingly, the present invention is neither restricted to passivation of a semiconductor device nor to any typical operation temperature of such a device, but the invention will hereinafter be particularly thoroughly discussed with respect to problems arising when passivating a semiconductor device adapted to operate at high temperatures for illuminating but not in any way limiting the present invention.
The passivation of the semiconductor device is made for different reasons and using different means and it is crucial for a reliable device operation. It may consist of one or several layers of the same or different insulator materials. The primary function of the passivation is to stabilise and to improve electronic or photo-electronic device performance characteristics. Another is to serve as passive coating protecting and isolating the device from the ambient environment, especially to prevent moisture and ion migration which may damage the semiconductor layer. For achieving this several demands are put simultaneously on a good passivation material: it should stabilise the surface region of the device often together with other measures applied to the semiconductor surface region itself. The other measures relate to different techniques used to control and reduce the electric field and leakage current by means of controlling the doping in the semiconductor surface region and sometimes also structural and chemical properties of the semiconductor surface or its topography. It should contribute in smoothing out and reducing the electric field created in the surface region of the device during its operation. It should prevent moisture and ionic species reaching the surface by presenting an efficient diffusion barrier. The chemical bonding between said second layer next to the semiconductor layer and the semiconductor layer should not introduce interfacial charge of its own and the insulator should be free from mobile charges and polarisation effects. If possible, the passivation should shield the device from electrical fields and charges created by electrostatic discharge in the surrounding ambient. The passivating layer should also provide mechanical protection of the device surface.
In order to do all this the material of the passivation layer should have a high resistivity and a high breakdown strength as well as a low density of shallow and deep level interfacial and bulk traps. Shallow centra act as doping levels and may reduce the resistivity of the layer and deep centers may give rise to quasi-permanent charging of the passivation layer.
The demands set on a protecting, passivating or insulating layer are especially severe in semiconductor devices intended for high temperature operation. Such a layer should have good adhesion to the substrate (semiconductor layer) and be structurally compatible with the substrate. The properties of the passivating layer should be: as little as possible dependent on the temperature in the operational temperature range. The layer should especially preserve high resistivity and high breakdown strength at high temperatures. Closely matched thermal expansion coefficients of the material of the semiconductor layer and that of the passivating layer are required to prevent build-up of stresses in the semiconductor. The protecting layer may also otherwise xe2x80x9clet the gripxe2x80x9d to the semiconductor layer go when the temperature changes and be at least partially released from the latter. The passivating layer should also be mechanically, thermally and chemically stable in the entire operational range of the device. Furthermore, the passivating layer should have a good thermal conduction. If such a passivating layer is also highly resistant to the environmental influence it could open possibilities of greatly simplifying the encapsulation issues by relieving the demands for hermetic packaging.
It would also be preferred that such a passivating layer may be produced at low process temperatures while allowing only low energy of particles, such as ions, photons or electrons, to hit the semiconductor layer during the deposition process.
Moreover, the present invention is directed to semiconductor devices of all types of semiconductor material as said first material, but it is particularly directed to obtaining a passivation adapted to SiC as such semiconductor material, so that especially the properties of SiC to withstand high temperatures and high breakdown fields may be utilised. For passivating semiconductor devices of SiC it is known to use thermal silicon dioxide in combination with a layer of silicon nitride or in combination with a thick layer of silicon dioxide created by CVD (Chemical Vapour Deposition). However, silicon dioxide is not a satisfactory passivation material for silicon carbide, especially not at high temperatures. This is due to two reasons. One is the relatively low ratio between breakdown field of silicon dioxide and silicon carbide which in combination with the relation between the dielectric constants of both materials, brings the electric field in silicon dioxide to only about a factor two lower than the critical breakdown field of the best quality silicon dioxides when the field in silicon carbide is close to its maximum value. The second is a relatively small energy barrier between the silicon carbide and the silicon dioxide, which increases the probability of charge injection. Both factors combine and lead to drastically reduce dielectric strength and reliability of the silicon dioxide at elevated temperatures. Furthermore, silicon dioxide grown on SiC is contaminated by unremoved carbon and it""s structure is also probably disturbed by the volatile carbon compounds leaving the oxide during it""s formation, like CO and CO2. 
Other materials than silicon dioxide, such as substantially monocrystalline AlN (PCT/SE95/01596), having a substantially monocrystalline structure have also been proposed for passivating SiC-devices. These materials have, however, a risk of build-up of stresses should the lattice match at the interface not be nearly perfect.
The object of the present invention is to provide a semiconductor device of the type defined in the introduction, in which said protecting layer fulfils its function in a better way than such layers already known while to a large extent satisfying the demands put on such a layer mentioned above.
This object is according to the invention obtained by providing such a semiconductor device in which said second material has at least in one portion of said protecting layer a nano-crystalline and amorphous structure by being composed of crystalline grains with a size less than 100 nm and a resistivity at room-temperature exceeding 1xc3x971010 xcexa9cm.
Said nano-crystalline and amorphous structure of the second material will facilitate structural adjustment of the protecting layer to said first semiconductor layer preventing occurrence of mechanical stresses being the cause of poor adhesion, of occurrence of high concentration of electronic interface states leading in turn to charging phenomena and instabilities and of reduced resistance to mechanical and thermal stresses leading to for instance micro-cracks. In addition, the nano-crystalline and amorphous structure reduces the influence of grain boundaries, that constitute serious structural defects in the crystalline structures, on the properties of the layers. Another advantage of said nano-crystalline and amorphous structure is that it may be obtained by much lower process temperatures than mono-crystalline structures, such as for example Reactive Pulse Plasma method (RPP) at 25xc2x0 C. or Radio Frequency Plasma method (RFP) below 500xc2x0 C. Both plasma methods can also be combined in the same growth and deposition process. Important characteristics of the process are the specific process conditions as well as in situ substrate preparation procedures for pre-cleaning and pre-etching all necessary to obtain the best desired effect.
It is another object of the present invention to provide a semiconductor device defined in the introduction with a protecting layer that is thermally stable at different temperatures, especially at high temperatures, such as at the possible operation temperature of SiC (up to 900xc2x0 C.) and can withstand breakdown fields close to the physical limit of SiC (1-2 MV/cm).
This object is according to the invention obtained by providing such a device in which said second material has at least in one portion of said protecting layer a nano-crystalline and/or amorphous structure, whereas nano-crystalline structure is defined as composed of crystalline grains with a size less than 100 nm, and said second material is one or a combination of any member of the following group of compounds: AlN, GaN, CN, BN and NCD (Nano-Crystalline Diamond).
Such a second material for the protecting layer means a good adhesion to the SiC surface at high temperatures, good mechanical properties and good dielectric properties. It may also be created by said deposition techniques (RPP and RFP) at a low temperature regime. Accordingly, structural adjustment of the second material to the semiconductor material is facilitated by the amorphous and/or nano-crystalline structure preventing occurrence of mechanical stresses between the two layers being the cause of a lot of problems mentioned above.
According to a preferred embodiment of the invention said first material is adapted to enable an operation temperature of the semiconductor device of at least 200xc2x0 C. by being electrically stable at that temperature. Especially the nano-crystalline and/or amorphous structure property of said second material makes it well suited for such high temperature operation applications, since it will counteract problems of poor adhesion at higher temperatures due to slightly different coefficients of thermal expansion between the semiconductor material and said second material.
According to another preferred embodiment of the invention said first material is SiC. The invention is particularly suited for semiconductor devices having SiC as semiconductor material, since the properties of the material for said second layer are particularly advantageous for applications, in which the properties of SiC to withstand high temperatures and high electric fields may be utilised.
According to another preferred embodiment of the invention said protecting layer comprise at least two sub-layers, namely a thin poly- or monocrystalline first sub-layer forming an interface to said first semiconductor layer and a much thicker nano crystalline and/or amorphous second sub-layer on top thereof. xe2x80x9cThinxe2x80x9d does here preferably mean a thickness of a few atom layers. Such a thin layer with higher crystalline quality than the rest of the protecting layer may be of interest when a very good lattice match may be obtained between the semiconductor material and material used for said thin sub-layer and it may for such a material be automatically created even if a deposition technique with a low process temperature giving rise to a nano-crystalline or amorphous structure in the bulk of the protecting layer is used.
Such a thin layer with higher crystalline quality (or crystalline) may be SiC, AlN, CN, BN or diamond.
According to another preferred embodiment of the invention said protecting layer comprise at least two sub-layers, namely a thin amorphous first sub-layer forming an interface to said first semiconductor layer and a much thicker nano-crystalline and/or amorphous second sub-layer on top thereof. xe2x80x9cThinxe2x80x9d does here preferably mean a thickness of a few atom layers.
Such a thin amorphous layer have a structural composition that can be described as consisting of following compounds or a combination thereof SiO2, SiO, SiON, SiN being in the most simple cases a silicon dioxide or silicon oxynitride or silicon nitride.
According to another preferred embodiment of the invention said protecting layer comprise at least two sub-layers, namely a thin monocrystalline or amorphous first sub-layer forming an interface to said first semiconductor layer and a much thicker nano crystalline and/or amorphous second sub-layer on top thereof. xe2x80x9cThinxe2x80x9d does here preferably mean a thickness of one to 15 nm. Such a thin layer with higher bandgap than that of SiC will constitute a tunneling barrier for charge carriers between the SiC and the second sub-layer. The function of the first sub-layer is to provide a good and stable interface to the SiC characterised by low density of the interface states. While the function of the second sub-layer is to transport away or neutralise the charge carriers tunneling. through the barrier. Due to the fact that charge is tunneling through the first sub-layer it is not interacting with it in a way it would if the layer would be thick and the transport through it would occur by conduction. This means that there is no charge trapping in the first sub-layer and that the charge state of the passivation is controlled mainly by the second sub-layer.
Such a thin first sub-layer could be SiO2, SiC, AlN, BN, CN or (C) diamond, or metal oxide like for example Al2O3, Ta2O5, TiO, TiO2, MgO.
According to a preferred embodiment of the invention the main part of the protecting layer has a nano-crystalline and/or amorphous structure. Accordingly, substantially the entire protecting layer is purely amorphous, purely nano-crystalline or a combination thereof, which makes it well suited for use as encapsulation of the entire device, especially Multi Chip Modules and integrated circuits. Accordingly, such a protecting layer may effectively shield active parts of such devices and electronic circuits from the environment, which is of particular interest in the case of devices intended for high temperature operation and in combination with hostile environments that are destructive to both semiconductor devices and metallisation interconnections.
According to another preferred embodiment of the invention said device has a junction adapted to hold a voltage in a blocking state of the device and said protecting layer is adapted to passivate said junction, which may be a pn-junction, but also a Schottky-junction. This is particularly advantageous in combination with the group of compounds mentioned above, since the electric fields created in those materials will be remarkably lower than their critical electric field also when used in combination with SiC withstanding very high fields. The low density of interface states will contribute to the possibility to efficiently passivate such a junction for high electric fields.
Further advantages and advantageous features of the invention appear from the following description and the other dependent claims.